As semiconductor devices continue to become smaller and smaller, new techniques arise in achieving ever decreasing footprints for device functionality. Memory devices, especially, because there are many millions of identical cells in a single memory chip, are the focus of intensive miniaturization efforts.
Modern memory devices are employing characteristic feature sizes approaching 100 nm, with even smaller device sizes on the technology horizon. Continued shrinking pushes the limits of physics by putting features in such proximity that electrical isolation and electrical connection to cells is very difficult.
One of the techniques used to achieve the isolation such miniaturization requires is Shallow Trench Isolation (STI) which enables closer feature proximity on a chip than previously possible. Some memory devices, with millions of memory gates in a single chip, also employ trenches, or channels, to provide pathways for supplying connections to the sources (Vss) and drains of memory gates.
A flash or block erase memory (flash memory), such as Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. Programming occurs by hot electron injection in order to program the floating gate and a programming charge is typically stored in the floating gate between a tunnel oxide and a control gate. The programming charge is contained by an isolating layer which is often an oxide/nitride/oxide stack. Erasure employs Fowler-Nordheim tunneling effects in which electrons punch through the thin dielectric layer, thereby reducing the amount of charge on the floating gate. Erasing a cell generally sets the logical value of the cell to “1,” while programming a cell sets the logical value to “0.” The flash memory cell provides for nonvolatile data storage which remains stable without power for upwards of ten years.
Conventional Art FIG. 1 illustrates a typical configuration of a plan view of a section of a memory array, 100, in a common configuration for a memory device. Conventional Art FIG. 1 is not drawn to scale. As shown in Conventional Art FIG. 1, array 100 comprises rows 110 and columns 120 of memory cells. Each of the memory cells are isolated from other memory cells by insulating layers (e.g., a plurality of shallow trench isolation regions (STI) 112. The control gates of each of the memory cells are coupled together in each of the plurality of rows 110 of memory cells, and form a plurality of word lines 101 that extend along the row direction. Bit lines extend in the column direction and are coupled to drain regions via drain contacts 108, which are typically “vias” in an associated column of memory cells 120.
A plurality of source lines (Vss) 102 extend in the row direction and are coupled to, and comprise, the source regions of each of the memory cells in the array of memory cells 100. One source line provides the source regions in adjoining rows of memory cells, and as a result, one source region is shared between two memory cells. Similarly, drain regions are shared amongst adjoining rows of memory cells, and as a result, one drain region is shared between two memory cells.
Conventional art FIG. 1B, (Section A—A) illustrates the depth relationship between STI 112, source/Vss lines 102 and drains 118. As is illustrated in Conventional Art FIG. 1C, the source/Vss lines 102 are typically formed by ion implantation 150 in the silicon substrate of the memory device. The drain regions are also formed by ion implantation, 151. Because the source implantation must be formed in the substrate under the existing STI trench and between existing cells, the ion energies required are very large, on the order of 2e15 eV. In order to provide a continuous source line, the implantation bean must be angled to provide implantation in the STI trench walls. The angles are on the order of twenty degrees from vertical. The large implantation energies also form the conductive extension of the source regions under the memory cells. As cell sizes shrink, the insulative region between source and drain, 161, can narrow to the point of shorting the memory cell.
What is needed, then, is a method for forming a Vss connection that provides the requisite continuity between source regions without shrinking the isolation between source and drain. Furthermore, the method must be achievable using existing manufacturing methods.